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NM93C56 2048-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus)
February 2000
NM93C56 2048-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus)
General Description
NM93C56 is a 2048-bit CMOS non-volatile EEPROM organized as 128 x 16-bit array. This device features MICROWIRE interface which is a 4-wire serial bus with chipselect (CS), clock (SK), data input (DI) and data output (DO) signals. This interface is compatible to many of standard Microcontrollers and Microprocessors. There are 7 instructions implemented on the NM93C56 for various Read, Write, Erase, and Write Enable/Disable operations. This device is fabricated using Fairchild Semiconductor floating-gate CMOS process for high reliability, high endurance and low power consumption. "LZ" and "L" versions of NM93C56 offer very low standby current making them suitable for low power applications. This device is offered in both SO and TSSOP packages for small space considerations.
Features
I Wide VCC 2.7V - 5.5V I Typical active current of 200A 10A standby current typical 1A standby current typical (L) 0.1A standby current typical (LZ) I No Erase instruction required before Write instruction I Self timed write cycle I Device status during programming cycles I 40 year data retention I Endurance: 1,000,000 data changes I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
Functional Diagram
CS SK DI INSTRUCTION REGISTER
VCC INSTRUCTION DECODER CONTROL LOGIC AND CLOCK GENERATORS
ADDRESS REGISTER
HIGH VOLTAGE GENERATOR AND PROGRAM TIMER
DECODER
EEPROM ARRAY 16
READ/WRITE AMPS 16 VSS
DATA IN/OUT REGISTER 16 BITS DO DATA OUT BUFFER
(c) 2000 Fairchild Semiconductor International NM93C56 Rev. E
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NM93C56 2048-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus)
Connection Diagram
Dual-In-Line Package (N) 8-Pin SO (M8) and 8-Pin TSSOP (MT8)
CS SK DI DO 1 2 3 4 8 7 6 5
VCC NC NC GND
Top View Package Number N08E, M08A and MTC08
Pin Names
CS SK DI DO GND NC VCC Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground No Connect Power Supply
NOTE: Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the VCC applied to the device. This will ensure proper operation.
Ordering Information NM 93 C XX LZ E XXX
Package N M8 MT8 None V E Blank L LZ 56 C CS Interface 93
Letter Description
8-pin DIP 8-pin SO 8-pin TSSOP 0 to 70C -40 to +125C -40 to +85C 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V and <1A Standby Current 2048 bits CMOS Data protect and sequential read MICROWIRE
Temp. Range
Voltage Operating Range
Density
Fairchild Memory Prefix
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NM93C56 2048-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus)
Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 sec.) ESD rating -65C to +150C +6.5V to -0.3V
Operating Conditions
Ambient Operating Temperature NM93C56 NM93C56E NM93C56V Power Supply (VCC) 0C to +70C -40C to +85C -40C to +125C 4.5V to 5.5V
+300C 2000V
DC and AC Electrical Characteristics VCC = 4.5V to 5.5V unless otherwise specified
Symbol
ICCA ICCS IIL IOL VIL VIH VOL1 VOH1 VOL2 VOH2 fSK tSKH tSKL tSKS tCS tCSS tDH tDIS tCSH tDIH tPD tSV tDF tWP
Parameter
Operating Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage SK Clock Frequency SK High Time SK Low Time SK Setup Time Minimum CS Low Time CS Setup Time DO Hold Time DI Setup Time CS Hold Time DI Hold Time Output Delay CS to Status Valid CS to DO in Hi-Z Write Cycle Time
Conditions
CS = VIH, SK=1.0 MHz CS = VIL VIN = 0V to VCC (Note 2)
Min
Max
1 50 -1
Units
mA A A V V V MHz ns ns ns ns ns ns ns ns ns
-0.1 2 IOL = 2.1 mA IOH = -400 A IOL = 10 A IOH = -10 A (Note 3) 0C to +70C -40C to +125C 250 300 250 50 (Note 4) 250 100 70 100 0 20 2.4
0.8 VCC +1 0.4 0.2
VCC - 0.2 1
500 500 CS = VIL 100 10
ns ns ns ms
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NM93C56 2048-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus)
Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 sec.) ESD rating -65C to +150C +6.5V to -0.3V
Operating Conditions
Ambient Operating Temperature NM93C56L/LZ NM93C56LE/LZE NM93C56LV/LZV Power Supply (VCC) 0C to +70C -40C to +85C -40C to +125C 2.7V to 5.5V
+300C 2000V
DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified
Symbol
ICCA ICCS
Parameter
Operating Current Standby Current L LZ (2.7V to 4.5V) Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage SK Clock Frequency SK High Time SK Low Time SK Setup Time Minimum CS Low Time CS Setup Time DO Hold Time DI Setup Time CS Hold Time DI Hold Time Output Delay CS to Status Valid CS to DO in Hi-Z Write Cycle Time
Conditions
CS = VIH, SK=1.0 MHz CS = VIL
Min
Max
1 10 1
Units
mA A A A V V KHz s s s s s ns s ns s
IIL IOL VIL VIH VOL VOH fSK tSKH tSKL tSKS tCS tCSS tDH tDIS tCSH tDIH tPD tSV tDF tWP
VIN = 0V to VCC (Note 2) -0.1 0.8VCC IOL = 10A IOH = -10A (Note 3) 0.9VCC 0 1 1 0.2 (Note 4) 1 0.2 70 0.4 0 0.4
1 0.15VCC VCC +1 0.1VCC 250
2 1 CS = VIL 0.4 15
s s s ms
Capacitance TA = 25C, f = 1 MHz (Note 5)
Symbol
COUT CIN
Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: Typical leakage values are in the 20nA range.
Test
Output Capacitance Input Capacitance
Typ
Max
5 5
Units
pF pF
Note 3: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter). Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation. Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode diagram on the following page.)
AC Test Conditions
VCC Range
(Extended Voltage Levels)
Note 5:
This parameter is periodically sampled and not 100% tested.
VIL/VIH Input Levels
0.3V/1.8V 0.4V/2.4V
VIL/VIH Timing Level
1.0V 1.0V/2.0V
VOL/VOH Timing Level
0.8V/1.5V 0.4V/2.4V
IOL/IOH
10A 2.1mA/-0.4mA
2.7V VCC 5.5V
(TTL Levels)
4.5V VCC 5.5V
Output Load: 1 TTL Gate (CL = 100 pF)
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NM93C56 2048-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus)
Pin Description
Chip Select (CS)
This is an active high input pin to NM93C56 EEPROM (the device) and is generated by a master that is controlling the device. A high level on this pin selects the device and a low level deselects the device. All serial communications with the device is enabled only when this pin is held high. However this pin cannot be permanently tied high, as a rising edge on this signal is required to reset the internal state-machine to accept a new cycle and a falling edge to initiate an internal programming after a write cycle. All activity on the SK, DI and DO pins are ignored while CS is held low.
Microwire Interface
A typical communication on the Microwire bus is made through the CS, SK, DI and DO signals. To facilitate various operations on the Memory array, a set of 7 instructions are implemented on NM93C56. The format of each instruction is listed under Table 1.
Instruction
Each of the 7 instructions is explained under individual instruction descriptions.
Start bit
This is a 1-bit field and is the first bit that is clocked into the device when a Microwire cycle starts. This bit has to be "1" for a valid cycle to begin. Any number of preceding "0" can be clocked into the device before clocking a "1".
Serial Clock (SK)
This is an input pin to the device and is generated by the master that is controlling the device. This is a clock signal that synchronizes the communication between a master and the device. All input information (DI) to the device is latched on the rising edge of this clock input, while output data (DO) from the device is driven from the rising edge of this clock input. This pin is gated by CS signal.
Opcode
This is a 2-bit field and should immediately follow the start bit. These two bits (along with 2 MSB of address field) select a particular instruction to be executed.
Serial Input (DI)
This is an input pin to the device and is generated by the master that is controlling the device. The master transfers Input information (Start bit, Opcode bits, Array addresses and Data) serially via this pin into the device. This Input information is latched on the rising edge of the SCK. This pin is gated by CS signal.
Address Field
This is an 8-bit field and should immediately follow the Opcode bits. In NM93C56, only the LSB 7 bits are used for address decoding during READ, WRITE and ERASE instructions. During these three instructions (READ, WRITE and ERASE), the MSB is "don't care" (can be 0 or 1). During all other instructions, the MSB 2 bits are used to decode instruction (along with Opcode bits).
Serial Output (DO)
This is an output pin from the device and is used to transfer Output data via this pin to the controlling master. Output data is serially shifted out on this pin from the rising edge of the SCK. This pin is active only when the device is selected.
Data Field
This is a 16-bit field and should immediately follow the Address bits. Only the WRITE and WRALL instructions require this field. D15 (MSB) is clocked first and D0 (LSB) is clocked last (both during writes as well as reads).
Table 1. Instruction set Instruction
READ WEN WRITE WRALL WDS ERASE ERAL
Start Bit
1 1 1 1 1 1 1
Opcode Field
10 00 01 00 00 11 00 X 1 X 0 0 X 1 A6 1 A6 1 0 A6 0
Address Field
A5 X A5 X X A5 X A4 X A4 X X A4 X A3 X A3 X X A3 X A2 X A2 X X A2 X A1 X A1 X X A1 X A0 X A0 X X A0 X
Data Field
D15-D0 D15-D0
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NM93C56 2048-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus)
Functional Description
A typical Microwire cycle starts by first selecting the device (bringing the CS signal high). Once the device is selected, a valid Start bit ("1") should be issued to properly recognize the cycle. Following this, the 2-bit opcode of appropriate instruction should be issued. After the opcode bits, the 8-bit address information should be issued. For certain instructions, some of these 8 bits are don't care values (can be "0" or "1"), but they should still be issued. Following the address information, depending on the instruction (WRITE and WRALL), 16-Bit data is issued. Otherwise, depending on the instruction (READ), the device starts to drive the output data on the DO line. Other instructions perform certain control functions and do not deal with data bits. The Microwire cycle ends when the CS signal is brought low. However during certain instructions, falling edge of the CS signal initiates an internal cycle (Programming), and the device remains busy till the completion of the internal cycle. Each of the 7 instructions is explained in detail in the following sections.
The status of the internal programming cycle can be polled at any time by bringing the CS signal high again, after tCS interval. When CS signal is high, the DO pin indicates the READY/BUSY status of the chip. DO = logical 0 indicates that the programming is still in progress. DO = logical 1 indicates that the programming is finished and the device is ready for another instruction. It is not required to provide the SK clock during this status polling. While the device is busy, it is recommended that no new instruction be issued. Refer Write cycle diagram. It is also recommended to follow this instruction (after the device becomes READY) with a Write Disable (WDS) instruction to safeguard data against corruption due to spurious noise, inadvertent writes etc.
4) Write All (WRALL)
Write all (WRALL) instruction is similar to the Write instruction except that WRALL instruction will simultaneously program all memory locations with the data pattern specified in the instruction. This instruction is valid only when I Device is write-enabled (Refer WEN instruction) Input information (Start bit, Opcode, Address and Data) for this WRALL instruction should be issued as listed under Table1. After inputting the last bit of data (D0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. It takes tWP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. Status of the internal programming can be polled as described under WRITE instruction description. While the device is busy, it is recommended that no new instruction be issued. Refer Write All cycle diagram.
1) Read (READ)
READ instruction allows data to be read from a selected location in the memory array. Input information (Start bit, Opcode and Address) for this instruction should be issued as listed under Table1. Upon receiving a valid input information, decoding of the opcode and the address is made, followed by data transfer from the selected memory location into a 16-bit serial-out shift register. This 16-bit data is then shifted out on the DO pin. D15 bit (MSB) is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit (logical 0) precedes this 16-bit data output string. Output data changes are initiated on the rising edge of the SK clock. After reading the 16-bit data, the CS signal can be brought low to end the Read cycle. Refer Read cycle diagram.
2) Write Enable (WEN)
When VCC is applied to the part, it "powers up" in the Write Disable (WDS) state. Therefore, all programming operations must be preceded by a Write Enable (WEN) instruction. Once a Write Enable instruction is executed, programming remains enabled until a Write Disable (WDS) instruction is executed or VCC is completely removed from the part. Input information (Start bit, Opcode and Address) for this WEN instruction should be issued as listed under Table1. The device becomes write-enabled at the end of this cycle when the CS signal is brought low. Execution of a READ instruction is independent of WEN instruction. Refer Write Enable cycle diagram.
5) Write Disable (WDS)
Write Disable (WDS) instruction disables all programming operations and should follow all programming operations. Executing this instruction after a valid write instruction would protect against accidental data disturb due to spurious noise, glitches, inadvertent writes etc. Input information (Start bit, Opcode and Address) for this WDS instruction should be issued as listed under Table1. The device becomes write-disabled at the end of this cycle when the CS signal is brought low. Execution of a READ instruction is independent of WDS instruction. Refer Write Disable cycle diagram.
6) Erase (ERASE)
The ERASE instruction will program all bits in the specified location to a logical "1" state. Input information (Start bit, Opcode and Address) for this WDS instruction should be issued as listed under Table1. After inputting the last bit of data (A0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. It takes tWP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. Status of the internal programming can be polled as described under WRITE instruction description. While the device is busy, it is recommended that no new instruction be issued. Refer Erase cycle diagram.
3) Write (WRITE)
WRITE instruction allows write operation to a specified location in the memory with a specified data. This instruction is valid only when I Device is write-enabled (Refer WEN instruction) Input information (Start bit, Opcode, Address and Data) for this WRITE instruction should be issued as listed under Table1. After inputting the last bit of data (D0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. It takes tWP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction.
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NM93C56 2048-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus)
7) Erase All (ERAL)
The Erase all instruction will program all locations to a logical "1" state. Input information (Start bit, Opcode and Address) for this WDS instruction should be issued as listed under Table1. After inputting the last bit of data (A0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. It takes tWP time (Refer appropriate DC and AC Electrical Characteristics table) for the internal programming cycle to finish. During this time, the device remains busy and is not ready for another instruction. Status of the internal programming can be polled as described under WRITE instruction description. While the device is busy, it is recommended that no new instruction be issued. Refer Erase All cycle diagram.
Note: The Fairchild CMOS EEPROMs do not require an "ERASE" or "ERASE ALL" instruction prior to the "WRITE" or "WRITE ALL" instruction, respectively. The "ERASE" and "ERASE ALL" instructions are included to maintain compatibility with earlier technology EEPROMs.Clearing of Ready/Busy status
When programming is in progress, the Data-Out pin will display the programming status as either BUSY (low) or READY (high) when CS is brought high (DO output will be tri-stated when CS is low). To restate, during programming, the CS pin may be brought high and low any number of times to view the programming status without affecting the programming operation. Once programming is completed (Output in READY state), the output is `cleared' (returned to normal tri-state condition) by clocking in a Start Bit. After the Start Bit is clocked in, the output will return to a tri-stated condition. When clocked in, this Start Bit can be the first bit in a command string, or CS can be brought low again to reset all internal circuits. Refer Clearing Ready Status diagram.
Related Document
Application Note: AN758 - Using Fairchild's MICROWIRETM EEPROM.
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NM93C56 2048-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus)
Timing Diagrams
SYNCHRONOUS DATA TIMING
CS tSKS tCSS tSKH
SK
DI
DO (Data Read)
DO (Status Read)
; ;; ;;; ;; ;; ; ; ;; ;; ; ;;;;; ; ;; ; ;;;;;; ;;;;;;;; ; ; ;;;;;; ;;;;;;;; ; ;;;;;;; ;;;;;;;; ; ; ;;;;;;; ;;;;;;;;; ;;
tSKL tDIS tDIH Valid Input tPD tSV
Valid Input
Valid Output
; ; ; ;; ; ;; ; ;; ; ; ;;;;;;;;;;;;;;;;;;; ;; ; ;;;;;;;;;;;;;;;;;;;;; ;;;;;; ;;;;;;;; ; ; ; ;;;;;; ;;;;;;;; ; ;
tCSH tDH tPD tDF Valid Output tDF Valid Status
READ CYCLE (READ)
tCS CS
SK DI 1
Star t Bit
1
0
A7
A6
Address Bits(8)
A1
A0
Opcode Bits(2)
DO
High - Z
Dummy Bit
93C56: Address bits patter n -> 0-A6-A5-A4-A3-A2-A1-A0; (A6-A0 -> User defined)
;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;; ;;;
0 D15 D1 D0
WRITE ENABLE CYCLE (WEN)
tCS CS
SK DI 1
Star t Bit
0
0
A7
A6
Address Bits(8)
A1
A0
Opcode Bits(2)
DO
High - Z
93C56: A d d r e s s b i t s p a t t e r n - > 1 - 1 - x - x - x - x - x - x ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 )
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NM93C56 2048-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus)
Timing Diagrams (Continued)
WRITE DISABLE CYCLE (WDS)
tCS CS
SK DI 1
Star t Bit
0
0
A7
A6
Address Bits(8)
A1
A0
Opcode Bits(2)
DO
High - Z
93C56: A d d r e s s b i t s p a t t e r n - > 0 - 0 - x - x - x - x - x - x ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 )
WRITE CYCLE (WRITE)
tCS CS
SK DI 1
Star t Bit
0
1
A7
A6
Address Bits(8)
A1
A0
D15 D14
Data Bits(16)
D1
D0 tWP Ready Busy
Opcode Bits(2)
DO
High - Z
93C56: Address bits patter n -> 0-A6-A5-A4-A3-A2-A1-A0; (A6-A0 -> User defined) Data bits patter n -> User defined
WRITE ALL CYCLE (WRALL)
tCS CS
SK DI 1
Star t Bit
0
0
A7
A6
Address Bits(8)
A1
A0
D15 D14
Data Bits(16)
D1
D0 tWP Ready Busy
Opcode Bits(2)
DO
High - Z
93C56: A d d r e s s b i t s p a t t e r n - > 0 - 1 - x - x - x - x - x - x ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 ) Data bits pattern -> User defined
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NM93C56 2048-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus)
Timing Diagrams (Continued)
ERASE CYCLE (ERASE)
tCS CS
SK DI 1
Star t Bit
1
1
A7
A6
Address Bits(8)
A1
A0 tWP Ready Busy
Opcode Bits(2)
DO
High - Z
93C56: Address bits pattern -> 0-A6-A5-A4-A3-A2-A1-A0; (A6-A0 -> User defined)
ERASE ALL CYCLE (ERAL)
tCS CS
SK DI 1
Star t Bit
1
1
A7
A6
Address Bits(8)
A1
A0 tWP Ready Busy
Opcode Bits(2)
DO
High - Z
93C56: Address bits patter n -> 1-0-x-x-x-x-x-x ; (x -> Don't Care, can be 0 or 1)
CLEARING READY STATUS
CS
SK DI
Star t Bit
DO
High - Z Busy
Ready
High - Z
Note: This Star t bit can also be par t of a next instr uction. Hence the cycle can be continued (instead of getting ter minated, as shown) as if a new instr uction is being issued.
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NM93C56 2048-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197 (4.800 - 5.004)
8765
0.228 - 0.244 (5.791 - 6.198)
1234
Lead #1 IDENT 0.150 - 0.157 (3.810 - 3.988) 8 Max, Typ. All leads 0.04 (0.102) All lead tips
0.010 - 0.020 x 45 (0.254 - 0.508)
0.053 - 0.069 (1.346 - 1.753)
0.004 - 0.010 (0.102 - 0.254) Seating Plane
0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads
0.016 - 0.050 (0.406 - 1.270) Typ. All Leads
0.014 (0.356) 0.050 (1.270) Typ 0.014 - 0.020 Typ. (0.356 - 0.508)
Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8) Package Number M08A
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NM93C56 2048-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122 (2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ 0.169 - 0.177 (4.30 - 4.50) (1.78) Typ (0.42) Typ (0.65) Typ
0.246 - 0.256 (6.25 - 6.5)
0.123 - 0.128 (3.13 - 3.30)
1
4
Pin #1 IDENT
Land pattern recommendation
0.0433 Max (1.1) 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) Typ.
See detail A
0.0035 - 0.0079
0.0075 - 0.0098 (0.19 - 0.30)
0-8
Gage plane
DETAIL A Typ. Scale: 40X
0.020 - 0.028 (0.50 - 0.70) Seating plane
0.0075 - 0.0098 (0.19 - 0.25)
Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP, JEDEC (MT8) Package Number MTC08
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NM93C56 2048-Bit Serial CMOS EEPROM (MICROWIRETM Synchronous Bus)
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) 0.092 DIA (2.337) Pin #1 IDENT Option 1
0.032 0.005
8
7
8
+
7
6
5
0.250 - 0.005 (6.35 0.127)
(0.813 0.127) RAD Pin #1 IDENT
1 1 2 3 4
0.039 (0.991) 0.130 0.005 (3.302 0.127) Option 2 0.145 - 0.200 (3.683 - 5.080)
0.280 MIN (7.112) 0.300 - 0.320 (7.62 - 8.128)
0.040 Typ. (1.016) 0.030 MAX (0.762) 20 1
95 5 0.009 - 0.015 (0.229 - 0.381) +0.040 0.325 -0.015 +1.016 8.255 -0.381 0.125 (3.175) DIA NOM
0.065 (1.651)
0.125 - 0.140 (3.175 - 3.556) 90 4 Typ 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) 0.060 (1.524)
0.020 (0.508) Min
0.045 0.015 (1.143 0.381) 0.050 (1.270)
Molded Dual-In-Line Package (N) Package Number N08E
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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NM93C56 Rev. E
www.fairchildsemi.com

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